1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor apparatus and the semiconductor apparatus.
2. Description of the Related Art
In recent years, in order to achieve high integration and high functionality of semiconductor devices, enhancement of operation speed of device and increase of memory capacity are required. Recently, a COC (Chip on Chip) device in which a logic chip and a large-capacity DRAM are built up has also been developed as a substitute for an eDRAM (Embedded Dynamic Random Access Memory) chip.
Normally, in a COC device, solder bumps, gold bumps and the like are used for connecting chips to each other. In addition, bonding wires and relocation wirings such as gold (Au) plated wiring and copper (Cu) plated wiring are used for a power supply and the like in COC connected chips. Wiring interval becomes narrower and the diameter of the solder bump becomes smaller as the high integration of semiconductor device advances. Therefore, when performing connections using relocation wirings of Cu plated wiring and using solder bumps, there is a problem that wiring resistance and resistance between chips increases. There has been a need to reduce these resistances.
A technology related to such relocation wiring or forming a solder bump, for example, has been disclosed in JP-A 2006-237159 (KOKAI). In this technology, a resist mask having an opening is formed on a conducting layer on a wafer, and a plating film is formed inside the opening by using the technique of plating by supplying current to the conducting layer to form relocation wiring or a solder bump of the plating film.
However, the technique described in JP-A 2006-237159 (KOKAI) is too complicated. Because, when forming relocation wiring and a solder bump, patterning had to be performed on the resists beforehand, respectively, and then the relocation wiring and the solder bump were plated on the opening portion of the pattern.